搜索资源列表
ledwatertest
- 一个用verilog 编写的流水灯程序，对于初学者比较有用，主要用于理解状态机转换。-Written in a flowing light with verilog program more useful for beginners, mainly for the understanding of the state machine transition.
verilogshiyansoure37
- verilog实验的基本程序，包括状态机、数码管、流水灯、蜂鸣器、点阵、键盘等等，超详细的程序、适合初学者-verilog basic experimental procedures, including the state machine, digital control, water lights, buzzers, dot matrix, keyboard, etc., super detailed procedures, suitable for beginners
State-machine
- 实现了一个简单状态机的转换功能，用Verilog语言。-State machine implements a simple conversion function, with the Verilog language.
cheweideng
- 用Verilog语言编写的车尾灯，用状态机来实现，3个LED显示左转，3个LED显示右转，6个灯显示刹车-Using Verilog language taillights, the state machine to achieve, three LED display left, three right LED display, six brake light display
how-to-use-state-machine
- 三段式状态机的用法，对于想学习verilog及VHDL编程的人来说是必看的内容-The use of three-state machine, for those who want to learn verilog and VHDL programming is a must-see content people
three_machine_study
- verilog 三段式状态机的写法，很好的Pdf-verilog three-state machine is written, a good Pdf
VerilogDesignand-test_PdfPCode
- Verilog 设计与验证源码+PDF，经典教程，对与RTL和状态机的理解有很大帮助，适合FPGA开发工程师。-Verilog design and verification source+ PDF, classic tutorial, and state machine understanding of RTL helps a lot, suitable for the FPGA development engineers.
state-machine-design
- Verilog and VHDL状态机设计，内含源代码，希望对大家有所帮助。-Verilog and VHDL state machine design, including source code, we want to help.
Integrator-comb_timing-state
- 积分梳状滤波器和时序状态机的Verilog语言描述，适合硬件描述初学者-Integrator-comb filter and timing the Verilog language to describe state machines, hardware descr iption suitable for beginners
mealy_sequence
- 实现米粒状态机 用verilog语言实现状态机的过程-Implement a state machine with a grain of rice verilog state machine language course
cpu_fsm.tar
- cpu的verilog的不同状态的状态机实现程序编写-write or reset or read or delay of CPU by verilog
Nixie-tube
- 这是一个verilog HDL语言代码，主要利用状态机控制数码管，从0到9循环显示。-This is a verilog HDL language code, the main use state machine control digital tube, from 0 to 9 cyclic display.
ThBird
- 雷鸟车尾灯设计，采用VERILOG语言开发，大家可以逐渐熟悉状态机实验。-Thunderbird car taillight design, using VERILOG language, everyone can become familiar with the state machine experiment.
ps_top
- verilog写ps2接口驱动程序，对状态机的描述。把键盘串行的13为数据转换为并行的8为数据，并储存在寄存器-The needle verilog write ps2 interface drivers, to the descr iption of the state machine. The keyboard for data transfer of serial and parallel for the 8 for data, and stored in a register to xi
I8251A
- Verilog 异步串行收发器，收发器的设计，时序状态机的代码编写
Frame-synchronizer-
- 原创，帧同步器的Verilog代码，在FPGA上验证实现过，无误。作为通信系统帧传输的仿真，有限状态机同步态和失步态的切换仿真。-Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine sync
FPGA_ps2_lcd
- FPGA实现 LCD1602 显示 PS/2 键盘的键值,熟悉并掌握液晶 1602 显示屏的使用方法及PS/2键盘的接口标准，学习利用Verilog-HDL语言编写有限状态机实现较为复杂的设计与应用。-LCD1602 FPGA realizing that the PS/2 keyboard keys, familiar with and master the use of liquid crystal display 1602 method and PS/2 keyboard interfac
state
- verilog 应用状态机设计的序列检测器-verilog ，state machine
11111
- 1、用FPGA/CPLD实现HS162字符液晶显示。 2、分析相应的功能要求，分析CPLD与字符液晶HS162的接口典型电路。 3、利用状态机的设计方法，通过指令编程实现对HS162-4液晶模块的读/写操作，以及屏幕和光标的操作。 4、编写模块的Verilog HDL语言的设计程序。 5、在Quartus II软件或其他EDA软件上完成设计和仿真。 -This design of a CPLD-based controls HS162 to achieve character
Moore_Asynchronous_state_machine
- moore异步状态机verilog实现，通过异步时钟和两个输入来对输出的状态进行控制，比同步状态机有更广泛的应用。-the moore asynchronous state machine verilog implementation, asynchronous clock and two input to the output state control, have a much wider application than the synchronous state machine.